The present invention relates to a voltage pump circuit having an independent well-bias voltage, and more particularly to a pump circuit, wherein, in a pump circuit using a PMOS transistor as a transfer transistor, well-bias is applied to the transfer transistor with an independent voltage to allow for a stable pumping operation.
A conventional voltage pump circuit was disclosed in a thesis entitled: "Application of a High Voltage Pumped Supply for Low-power DRAM", R. C. Foss et al., 1992 Symposium on VLSI Circuits Digest of Technical Papers, pages 106-107, 1992.
One example of the conventional voltage pump circuit is illustrated in FIG. 1, which includes a level shifter 10 for controlling a gate of a transfer transistor MP4 with voltages of a ground voltage Vss and a boosted voltage Vpp, and a non-overlap circuit 20 for blocking an overlapping of a pumping time and a charge transfer time. In addition, a voltage pumping section 30, for pumping the voltage while precharging/pumping a charge to/from a pumping capacitor, is provided.
Level shifter 10 is formed such that a gate of PMOS transistor MP1 is supplied indirectly with boosted voltage Vpp via a drain of PMOS transistor MP2. The boosted voltage Vpp is directly connected to a source of a PMOS transistor MP2. A gate of PMOS transistor MP2 is indirectly supplied with boosted voltage Vpp via the drain of the transistor MP1. The source of the PMOS transistor MP1 is directly connected to Vpp. The drain of PMOS transistor MP1 is also indirectly connected to ground potential Vss via two NMOS transistors MN1 and MN2, and a drain of PMOS transistor MP2 is also indirectly connected to ground potential Vss via two NMOS transistors MN3 and MN4. Gates of NMOS transistors MN2 and MN3 are supplied with an internal power source Vint. A gate of NMOS transistor MN1 is connected to an input pulse OSC via an inverter INV1. Input pulse OSC is directly connected to a gate of NMOS transistor MN4.
By this construction, when input pulse OSC is high, the boosted voltage level Vpp is obtained at the drain of PMOS transistor MP1, and the ground potential Vss is obtained at the drain of PMOS transistor MP2. If input pulse OSC is low, the ground potential Vss is obtained at the drain of PMOS transistor MP1, and the boosted voltage level Vpp is obtained at the drain of PMOS transistor MP2.
Non-overlap circuit 20 includes a NAND gate, a NOR gate and an inverter INV2 such that either one of two inputs of the NAND gate is connected with pulse input OSC, and the other input is connected with the drain of PMOS transistor MP1 of level shifter 10. Then, either one of two inputs of the NOR gate is connected with pulse input OSC, and the other input is connected to the drain of PMOS transistor MP2 of level shifter 10 via inverter INV2.
Voltage pumping section 30 includes a pumping capacitor C1, and a PMOS transistor MP3 having a drain connected to a first electrode of pumping capacitor C1 at node A, a source connected to power source Vdd and a gate connected to an output of the NAND gate of non-overlap circuit 20 at a node C. Also, a PMOS transistor MP4, having a drain connected to a second electrode of pumping capacitor C1 at a node B, a source connected to boosted voltage Vpp and a gate connected to a drain of PMOS transistor MP2 of level shifter 10, is provided. An NMOS transistor MN7 has a drain connected to the second electrode of pumping capacitor C1 at the node B, a source connected to power source Vdd, a gate connected to the output of the NAND gate of non-overlap circuit 20 at the node C. In addition to these, an NMOS transistor MN5 has a drain connected to the first electrode of pumping capacitor C1 at the node A, a gate connected to internal power source Vint, and a source connected to a drain of an NMOS transistor MN6. The NMOS transistor MN6 also has a source connected to ground potential Vss and a gate connected to an output of the NOR gate of non-overlap circuit 20 at a node D.
As shown in timing charts of FIG. 2, an operation the conventional pump circuit is classified into two steps of precharging the pumping capacitor C1 and pumping (or discharging) the precharged pumping capacitor.
First, in the precharge step, when the OSC signal is in the "low" state, both a node C being the output terminal of the NAND gate and a node D being the output terminal of the NOR gate go to the "high" state. Thus, NMOS transistors MN5, MN6 and MN7 are turned on to allow a node A to be the Vss level and a node B is charged to Vdd-V.sub.T which is low, i.e., less than V.sub.T of NMOS transistor MN7.
After the precharge is performed as described above, the pumping step is performed successively. When the OSC signal goes to the "high" state, and node C (being the output terminal of the NAND gate) and node D (being the output terminal of the NOR gate) go to the "low" state. Thus, NMOS transistors MN6 and MN7 are turned off, so that node A is in the floating state and instantaneously goes to the Vdd level together with the turning on of the PMOS transistor MP3. Consequently, the level of node B is raised by an amount Vdd to be 2 Vdd-V.sub.T. The NMOS transistor MN4 is turned on to apply the Vss level to the gate of PMOS transistor MP4 which, in turn, is turned on to raise the voltage of node B to the Vpp node.
While the pumping capacitor repeats the precharge and pumping via the above-described operation, the operation of raising the charge from the low potential level to the high potential level is continuously carried out.
In almost all semiconductor memory devices, a redundancy decoder is provided for using an additional cell when a word line is shorted out to the ground voltage Vss, thereby repairing the semiconductor chip. However, when such a word line (which had been shorted out to the Vss) has been inspected during an initial test of such a repaired chip using the foregoing conventional pump circuit, the Vpp level is lower than Vdd-V.sub.T. Consequently, a PN junction is forward-biased in the transfer transistor MP4, so that the transfer transistor MP4 cannot be operated as a transistor. The shorted-out state of the PN junction of the transfer transistor MP4 is continued, making it impossible to recover to normal operation.
Therefore, the shorted-out state of the PN junction of the transfer transistor MP4 causes electric power to be greatly dissipated and the Vpp level to not recover. Consequently, the semiconductor chip must be treated as being defective, thereby degrading production yield.